Regviz

NXP Semiconductors /MIMXRT1011 /IOMUXC /SW_MUX_CTL_PAD_GPIO_04

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_04

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MIMXRT1011/IOMUXC/SW_MUX_CTL_PAD_GPIO_04#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SAI1_TX_DATA00 of instance: SAI1

1 (ALT1): Select mux mode: ALT1 mux port: GPT1_CAPTURE2 of instance: GPT1

2 (ALT2): Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1

4 (ALT4): Select mux mode: ALT4 mux port: SPDIF_IN of instance: SPDIF

5 (ALT5): Select mux mode: ALT5 mux port: GPIOMUX_IO04 of instance: GPIOMUX
SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_04

Links

()

Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data